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-- File: Main.vhd -- Generated by MyHDL 0.8 -- Date: Sat Jun 8 19:26:57 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_08.all; entity Main is port ( a: in std_logic; b: in std_logic; c: in std_logic; x: out std_logic; y: out std_logic ); end entity Main; architecture MyHDL of Main is begin MAIN_ANDLOGIC: process (a, c, b) is variable temp: std_logic; begin temp := stdl((bool(a) and bool(b)) or bool(c)); x <= temp; y <= stdl((not bool(temp))); end process MAIN_ANDLOGIC; end architecture MyHDL;
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