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Plain Text, pasted on Sep 17:
module controller1(x,clk,rstn,y,z); 
input x; 

input clk; 

input rstn; 

output y; 

output z; 

 parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100; 

reg [2:0] PRState, NXState; 

reg y; 

assign z = ~y; 

always @ (PRState) begin 
if (PRState == S4) y = 1'b1; 

else y = 1'b0; 

 end 

always @ (posedge clk or negedge rstn) begin 
if (rstn == 1'b0) PRState = S0; 

else PRState = NXState; 

 end 

always @ (PRState or x) begin 
case (PRState) 

  S0 : if (x == 1'b0) NXState = S1; 

   else NXState = S0; 

  S1 : if (x == 1'b0) NXState = S2; 

   else NXState = S1; 

  S2 : if (x == 1'b1) NXState = S3; 

   else NXState = S2; 

  S3 : if (x == 1'b0) NXState = S4; 

   else NXState = S3; 

  S4 : NXState = S4; 

endcase 

 end 

endmodule 



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