C,
pasted
on Apr 22:
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#define ENABLE_BIT_DEFINITIONS
#include "iocan32.h"
#include "inavr.h"
#include "port.h"
#include "mb.h"
#include "mbport.h"
#include "fled.h"
/********************************************************************************
* defines
*******************************************************************************/
#define UART_BAUD_RATE 19200 /**< @brief Скорость шины модбас, на которой работаем */
#define UART_BAUD_CALC(UART_BAUD_RATE,F_OSC) \
( ( F_OSC ) / ( ( UART_BAUD_RATE ) * 16UL ) - 1 )
/********************************************************************************
* static
*******************************************************************************/
/**
* @brief Read enable
*
* @param portNum
*/
static void re (BOOL value)
{
if(value) PORTD &= ~(1<<7);
else PORTD |= (1<<7);
}
/**
* @brief Drive enable
*
* @param portNum порт
*/
static void de (BOOL value)
{
if(value) PORTD |= (1<<4);
else PORTD &= ~(1<<4);
}
/**
* @brief Инициализирует ноги Re и De, если такые есть. Включает режим read enable
*
* @param portNum порт
*/
static void initDeRe (void)
{
DDRD |= (1<<7)|(1<<4);
PORTD |= (1<<7)|(1<<4);
}
/********************************************************************************
* global
*******************************************************************************/
/**
* @brief Управление передчай\отправки
*
* @param xRxEnable
* @param xTxEnable
*/
void vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable )
{
if( xRxEnable )
{
re(1);
UCSR1B |= (1<<RXEN1);
}
else
{
re(0);
UCSR1B &= ~(1<<RXEN1);
}
if( xTxEnable )
{
de(1);
UCSR1B |= (1<<TXEN1);
}
else
{
de(0);
UCSR1B &= ~(1<<TXEN1);
}
}
/**
* @brief Инициализация уарта и портов RE и DE
*
* @param ucPORT порт
* @param ulBaudRate скорость
* @param ucDataBits количество бит данных
* @param eParity паритет
*
* @return TRUE on succes
*
*
*/
BOOL xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity )
{
/* prevent compiler warning. */
(void)ucPORT;
// 19200 8 bit 1 stop bit NO PARITI
UCSR1A=0x00;
UCSR1B=(1<<RXEN1)|(1<<TXEN1)|(1<<RXCIE1);
UCSR1C=(1<<UCSZ11)|(1<<UCSZ10);
UBRR1H=0x00;
UBRR1L=0x33;
initDeRe();
vMBPortSerialEnable( FALSE, FALSE );
return TRUE;
}
BOOL
xMBPortSerialPutByte( CHAR ucByte )
{
// while ( !(UCSR1A & (1<<UDRE1)) );
fledRed();
UDR1=ucByte;
return TRUE;
}
BOOL
xMBPortSerialGetByte( CHAR * pucByte )
{
*pucByte = UDR1;
return TRUE;
}
#pragma vector=USART1_TX_vect
__interrupt void uart1TxIrq (void)
{
pxMBFrameCBTransmitterEmpty( );
}
#pragma vector=USART1_RX_vect
__interrupt void uart1RxIrq (void)
{
pxMBFrameCBByteReceived( );
}
/********************************************************************************
* EOF
*******************************************************************************/
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Output:
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Line 20: error: iocan32.h: No such file or directory
Line 18: error: inavr.h: No such file or directory
Line 17: error: port.h: No such file or directory
Line 15: error: mb.h: No such file or directory
Line 19: error: mbport.h: No such file or directory
Line 17: error: fled.h: No such file or directory
Line 26: error: expected ')' before 'value'
Line 37: error: expected ')' before 'value'
In function 'initDeRe':
Line 50: error: 'DDRD' undeclared (first use in this function)
Line 50: error: (Each undeclared identifier is reported only once
Line 50: error: for each function it appears in.)
Line 51: error: 'PORTD' undeclared (first use in this function)
t.c: At top level:
Line 62: error: expected ')' before 'xRxEnable'
Line 99: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'xMBPortSerialInit'
Line 118: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'xMBPortSerialPutByte'
Line 127: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'xMBPortSerialGetByte'
Line 135: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'void'
Line 141: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'void'
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